|
Open Source Edition |
Evaluation Edition |
Enterprise Edition |
IP Function |
Basic Function |
Full Function |
Full Function |
IP Interface |
None |
AXI/APB |
AXI/APB |
Config Registers |
None |
Basic Register Set |
Full Register Set |
FPGA Demo Project |
YES |
YES |
YES |
Verification |
Low Coverage |
High Coverage |
High Coverage(Silicon/FPGA Proved) |
Verification Enviroment |
Simple |
Simple |
Complete |
Performance(Throughtput) |
Low |
High |
High |
Performance(Image/Video Quality) |
Low |
High |
High |
Performance (Compression Efficiency) |
Low |
High |
High |
Release IP |
RTL |
Encrypt Netlist |
Netlist/RTL/Cmodel |
Time Limited |
None |
YES (<20 minites) |
None |
Technical Support |
None |
None |
YES |
Image/Video Quality Tuning Support |
None |
None |
YES |
License Required |
None |
None |
YES |
Platform |
None |
FPGA(Platform Limited) |
FPGA/Silicon |